1. Field of the Invention
Embodiments of the present invention relate generally to the field of semiconductor devices. More particularly, embodiments of the present invention relate to improved semiconductor devices and improved fabrication techniques for semiconductor devices.
2. Description of the Related Art
As electronics continue toward greater miniaturization and faster processing speeds, various techniques have been developed for more compact packaging and increased transmission speeds in semiconductor chips. For example, because of its higher electrical conductance, copper is replacing aluminum as a material for making electrical connections between semiconductor devices or layers in semiconductor devices. One technique that has become widely adopted is the use of copper filled vias for making an electrical connection between the front and back sides of a chip or layers within a chip. Typically, the exposed copper protruding from the bottom of the chip is then soldered to a circuit board or another chip. This technique facilitates the stacking of chips and also shortens the interconnection between chip and other circuitry, compared to wire bonding techniques in which metal lines run along the top surface of the chip. Shortening the length of these electrical connections reduces RC delay and wire inductance, thereby increasing the signal transmission speed.
One of the challenges of forming a high quality copper via is that copper oxidizes very readily. If an oxide layer forms on the exposed surface of the copper, the oxide layer will interfere with the physical and electrical bonding of the copper to other metals and minimize the electrical conductance of the copper via. To ensure a good electrical connection, a plating process, such as Under Bump Metallization (UBM) process, is typically used to prevent the exposed copper from oxidizing. The metallization process adds additional cost to the fabrication of the chip and also presents an area of possible chip failure. For example, it has been found that tin plating over copper is susceptible to cracking. Additionally, the metallization process provides no corrosion protection for the copper sidewall within the via.
Therefore, it may be advantageous to provide an improved device and process for preventing corrosion of the metal within a metal-filled conductive via.